This invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit subjected to a test under application of a boosted voltage and a method for testing a semiconductor integrated circuit.
The semiconductor memory device such as a dynamic random access memory device has been enhanced in data storage capacity. This means that the manufacturer has increased the memory cells and the control lines associated with the memory cells. The manufacturer brings products of the semiconductor memory device to various tests before delivery to customers in order to guarantee the products. The manufacturer eliminates defective products from the products through the various tests, and can deliver non-defective products to the customers. Thus, the tests are important. However, the tests consume time and labor due to the large number of components to be tested. It is necessary for the manufacturer to simplify a testing method and accelerate the tests.
FIG. 1 shows a typical example of the semiconductor dynamic random access memory device with a built-in tester. Dynamic random access memory cells form a memory cell array MA, and word lines 501 are selectively connected to the dynamic random access memory cells. An external power voltage is applied to a power pin 201, and is supplied from the power pin 201 to a step-up circuit 2. The step-up circuit 2 is labeled with xe2x80x9cVBOOTxe2x80x9d, and boot-straps the external power voltage. Thus, the step-up circuit 2 generates an internal power voltage higher in magnitude than the external power voltage, and supplies the internal power voltage through a power supply line 202 to a row address decoder 3 and a word line driver 5. Thus, the row address decoder 3 and the word line driver 5 are powered with the internal power voltage.
A row address predecoded signal 301 is supplied to the row address decoder 3, and the row address decoder 3 supplies row address decoded signals to the word line driver 5. The word line driver 5 selectively changes the word lines 501 assigned a row address identical with the row address represented by the row address decoded signals to the internal power voltage level. For this reason, the step-up circuit 2 is designed to have a bootstrap capability, which satisfies the current driving capability of the word line driver 5 to push up the selected single word line 501 to the internal power voltage level. When the manufacturer brings products of the prior art semiconductor dynamic random access memory device to a test on the word lines 501, the word line driver 5 sequentially changes the word lines 501 to the internal power voltage, and the test requires a long time.
In order to shorten the time period consumed in the tests, the manufacturer carries out a burn-in test before separating a semiconductor wafer into chips, and a wafer burn-in test circuit 4 is incorporated in the prior art semiconductor dynamic random access memory device. The wafer burn-in test circuit 4 is enabled with an external enable signal 401. Then, the wafer burn-in test circuit 4 supplies a control signal 402 to the row address decoder 3. The row address decoder 3 is responsive to the control signal 402 so as to change all the decoded address signals to the active level. This results in that the word line driver 5 make all the word lines 501 concurrently go up to the internal power voltage. Thus, all of the word lines 501 are concurrently changed to the internal power voltage level, and the burn-in test is accelerated.
The word line driver 5 consumes a large amount of electric current in the concurrent activation of all the word lines 501. However, the step-up circuit 2 has the small bootstrap capability as described hereinbefore. In other words, the bootstrap capability is too short to concurrently push up all the word lines 501 to the internal power voltage. For this reason, an additional power supply pin 22 is added to the prior art semiconductor dynamic random access memory device (see FIG. 2), and an external power source (not shown) makes up a boosted voltage VBOOT as high as the internal power voltage through the power supply pin 22 to the power supply line 202 during the burn-in test. The additional power supply pin 22 is useless after the burn-in test. For this reason, the manufacturer covers the additional power supply pin 22 with synthetic resin in the molding stage so as not to project from the plastic package.
Recently, there is a request to carry out the burn-in test similar to that described hereinbefore after the molding stage. However, the additional power supply pin 22 has been already covered with the synthetic resin, and is not available for the burn-in test after the molding stage.
Following prior art documents have been found. The first prior art document is Japanese Patent Publication of Unexamined Application (laid-open) No. 9-7400, which was published on Jan. 10, 1997. A semiconductor memory device and a method for testing it are disclosed in Japanese Patent Publication of Unexamined Application No. 9-7400. Plural word lines and plural bit lines are concurrently selected from a set of word lines and a set of bit lines, and a test pattern is written into the memory cells connected to the selected word lines and the selected bit lines at a high speed. However, Japanese Patent Publication of Unexamined Application is silent to the burn-in test where all the word lines are concurrently activated.
Another prior art document is Japanese Patent Publication of Unexamined Application (laid-open) No. 8-153390, which was published on Jun. 11, 1996. The prior art document may less relate to the present invention. The prior art semiconductor integrated circuit disclosed therein has an output inverter. The prior art semiconductor integrated circuit is powered with a standard power voltage or a high power voltage. When the standard power voltage is selected, a boosted voltage is supplied from a boosting circuit to the output inverter. When the high power voltage is selected, the boosting circuit is disabled so as to prevent the output inverter from damage due to an extremely high power voltage produced through the boosting operation on the high power voltage. Thus, the teachings of Japanese Patent Publication of Unexamined Application 8-153390 does not relate to the word lines of a semiconductor dynamic random access memory device, nor to the burn-in test.
Yet another prior art document is PCT Application laid-open No. 10-512081, the International Publication Number of which was WO 96/13037. A smart power source for a flash memory is disclosed in PCT Application laid-open No. 10-512081. An external power voltage is supplied to an external power supply pin, and an internal boosting circuit is incorporated in the smart power source. A detector monitors the external power voltage. If the standard power voltage is supplied to the external power supply pin, the detector instructs the boosting circuit to distribute the boosted power voltage to other component circuits. However, if a high power voltage is supplied to the external power supply pin, the detector allows the high power voltage to be distributed to the other components. Thus, the teachings of PCT Application laid-open No. 10-512081 do not relate to the activation of word lines, nor the burn-in test.
It is therefore an important object of the present invention to provide a semiconductor integrated circuit device, which is brought to a test after a packaging with an external high power voltage.
It is also an important object of the present invention to provide a method for testing the semiconductor integrated circuit device.
To accomplish the object, the present invention proposes to provide a power transfer circuit in a semiconductor integrated circuit device for transferring the external high power voltage to an internal power supply line during a test after the packaging.
In accordance with one aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a first external pin applicable with an external standard power voltage when the semiconductor integrated circuit device forms a part of an electric system, a first step-up circuit connected to the first external pin and produces a first internal high power voltage from the external standard power voltage, internal circuits connected through an internal power supply line to the first step-up circuit so as to be powered with the first internal high power voltage, a second external pin applicable with an external high power voltage higher than the external standard power voltage in a test carried out after completion of a fabrication of the semiconductor integrated circuit device and a power transfer circuit connected between the second external pin and the internal power supply line and discriminating a request for the test so as to connect the second external pin to the internal power supply line in the test.
In accordance with another aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit device comprising the steps of applying an external high power voltage higher than an external standard voltage to an external pin, recognizing that a test is requested, transferring the external high power voltage through an internal power supply line to internal circuits and carrying a test under application of the external high power voltage to the internal circuits.